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STP2200ABGA
July 1997
USC
DATA SHEET DESCRIPTION
The Uniprocessor System Controller (USC) has a DRAM memory controller and functions to regulate the flow of requests and data on the UPA bus. It also controls the resets going to all UPA clients.
Uniprocessor System Controller
Features
* Controls up to eight standard SS-10/SS-20-type DRAM SIMMs * Supports various memory SIMM organizations: 16 MB, 64 MB, and 256 MB as well as dual-stacked 128-MB SIMMs * Controls and generates a number of resets for the system * Programmed via a standard 8-bit asynchronous interface (EBus) * JTAG interface allows full chip scan * 225-pin ABGA package
Benefits
* Standard workstation memory * Flexibility * High integration * Allows design of low-cost, low-chip-count embedded systems * Ease of design and testability * Low cost
The USC is used as the system controller of a complete Uniprocessor UltraSPARC system. Note: Instead of using the U2S, the USC can also be used with the UPA to PCI-bus; I/O interface controller (U2P)
UPA Devices
Abbreviations USC RIC U2S U2P XBI SC_UP RISC SYSIO Psycho BMX Part Number STP 2200ABGA STP2210QFP STP2220ABGA STP2222ABGA STP2230SOP Description Uniprocessor System Controller Reset/Interrupt/Clock Controller UPA to SBus I/O interface controller UPA to PCI bus I/O Interface controller Crossbar Data Path
Note: This data sheet refers to the UPA to System I/O interface. The UPA to PCI bus Interface controller (U2P) can be substituted where U2S appears.
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BLOCK AND TYPICAL APPLICATION DIAGRAMS
Chip Boundary UPA_ADDRBUS0[34:0] UPA_ADR0_PAR0 UPA_ADDR0_VAL0[1:0] UPA_SC_REQ0 UPA_REQIN0[1:0] UPA_ADDRBUS1[28:0] UPA_ADDR1_VAL1 UPA_PREPLY0[4:0] UPA_PREPLY1[4:0] UPA_PREPLY2[4:0] BMX_CMD[3:0] x2 UPA_SREPLY0[4:0] UPA_SREPLY1[4:0] SYS_RESET X_BUTTON_RESET P_BUTTON_RESET UPA_RESET0 UPA_RESET1 UPA_XIR EBUS_CS EBUS_RD EBUS_WR EBUS_RDY EBUS_ADDR[2:0] EBUS_DATA[7:0] JTAG EBus Interface JTAG_TCK JTAG_TMS JTAG_TDI JTAG_TDO JTAG_TRST Data Path Scheduler UPA_SREPLY2[4:0] UPA_ECC_VAL_0 UPA_DATA_STALL0 UPA_ECC_VAL_1 UPA_DATA_STALL1 Port Interface Memory Controller MEMADDR[12:0] RAS[3:0] CAS[3:0] WE MRB_CTRL[1:0] MWB_CTRL[1:0]
CLK + CLK - PLL_BYPASS Clock/PLL
Figure 1. USC Block Diagram
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STP2200ABGA
UPA_ADDRBUS1
UPA_64S 64 STP2220ABGA UPA-to-SBus Interface (U2S) or STP2xxxABGA UPA-to-PCI Interface (U2P) CPU 72 I/O Data Bus
UPA_ADDRBUS0
72
144 Processor Data Bus STP2200ABGA Uniprocessor System Controller (USC) BMX_CMD0[3:0] BMX_CMD1[3:0] MRB_CTRL MWB_CTRL STP2230SOP Crossbar Switch Array (18) (XB1)
288 Memory Data Bus
144 MEMADDR[12:0] RAS[3:0] CAS[3:0] WE Memory SIMMs
144
Figure 2. USC Typical Application Diagram
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SIGNAL DESCRIPTIONS
UPA Interface Signals
Signal UPA_ADDRBUS0[34:0] UPA_ADR0_PAR UPA_ADDR0_VAL[1:0] UPA_SC_REQ0 UPA_REQIN0[1:0] UPA_ADDRBUS1[28:0] UPA_ADDR1_VAL1 UPA_SREPLY0_[4:0] UPA_SREPLY1_[4:0] UPA_SREPLY2_[2:0] UPA_PREPLY0_[4:0] UPA_PREPLY1_[4:0] UPA_PREPLY2_[1:0] UPA_RESET0 UPA_RESET1 UPA_XIR UPA_ECC_VAL_0 UPA_ECC_VAL_1 UPA_DATA_STALL0 UPA_DATA_STALL1 I/O I/O I/O I/O O I O O O O O I I I O O O O O O O Address bus 0 (processor/U2S) Parity for address bus 0 [0] = processor, [1] = U2S USC request for address bus 0 Client address bus 0 arbitration requests: [0] = processor, [1] = U2S Address bus for UPA64S Address valid signal for UPA64S S_Reply for processor S_Reply for U2S S_Reply for UPA64S P_Reply from processor P_Reply from U2S P_Reply from UPA64S Reset for processor, tied to the U2S's UPA_ARB_RESET Reset for U2S XIR reset for processor only ECC valid for processor ECC valid for U2S Stall data to processor Stall data to U2S Description
Memory Interface Signals
Signal MEMADDR[12:0] RAS[3:0] CAS[3:0] WE I/O O O O O Row/column address RAS per SIMM pair CAS (four copies) Write enable Description
Crossbar Interface Signals
Signal BMX_CMD0[3:0] MRB_CTRL0 MWB_CTRL0 Type O O O Description Command to XB1 crossbar array of 18 devices Fill the XB1 read buffer Drain the XB1 write buffer
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Crossbar Interface Signals
Signal BMX_CMD1[3:0] MRB_CTRL1 MWB_CTRL1 Type O O O Duplicate of BMX_CMD0[3:0] Duplicate of MRB_CTRL0 Duplicate of MWB_CTRL0 Description
EBus Signals
Signal EBUS_DATA[7:0] EBUS_CS EBUS_ADDR[2:0] EBUS_RDY EBUS_WR EBUS_RD Type I/O I I O I I 5-V tolerant 5-V tolerant Condition 5-V tolerant 5-V tolerant 5-V tolerant Description Data in and data out pins - 3.3 volt output level Chip select for USC on the EBus EBus address EBus ready to the STP2001 SLAVIO- 3.3 volt output level Indicates write on EBus Indicates read on EBus
Miscellaneous Signals
Signal CLK+ CLK- SYS_RESET P_BUTTON_RESET X_BUTTON_RESET PLL_BYPASS JTAG_TDI JTAG_TDO JTAG_TCK JTAG_TMS JTAG_TRST DEBUG[3:0] PM_OUT Type I I I I I I I O I I I O O 5-V tolerant 5-V tolerant 5-V tolerant 5-V tolerant Condition PECL PECL 5-V tolerant 5-V tolerant 5-V tolerant System clock (differential) System clock (differential) Power-on reset; pulldown POR button reset XIR button reset Bypass internal PLL Test data input Test data output- 3.3 volt output level Scan clock Test mode select; pullup Reset TAP controller; pullup Debug pins Process monitor output Description
Power and Ground
Signal VDD VSS +3.3 V Ground Description
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Power and Ground
Signal PLL_VDD PLL_GND VCC Power for PLL Ground for PLL 5-V reference for 5-V tolerant inputs Description
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TECHNICAL OVERVIEW
The USC implements three UPA ports on two address buses. It has a programmable memory controller and an EBus interface. Addresses flow through the USC. Data flows through the crossbar switches.
UPA Port Interface (PIF)
The PIF is responsible for receiving UPA packets, decoding their destinations, and forwarding the packets to their proper destinations. The PIF also receives all P_Replys from UPA clients. UPA address bus 0 has two clients: the processor and U2S (UPA-to-SBus Interface), or U2P (UPA-to-PCI Interface). The PIF controls the arbitration on UPA address bus 0, for its two clients and itself. The two other masters on this bus are the processor and one of the system I/O devices. The PIF arbitration algorithm is described in the USC User Manual. Noncached transactions are typically forwarded to a system I/O chip. Cached transactions are typically forwarded to the memory controller. The PIF maintains data coherency in the system between the processor cache, main memory, and the U2S merge buffer. The UPA address bus 1 supports a single UPA64S device. This address bus is output only on the USC (for example: unidirectional), and the USC is always the master. This interface is typically used for a graphic slave device. The PIF will only generate and receive truncated P_Reply and S_Reply packets going to and coming from the UPA64s device. The PIF contains three sets of the following registers (one for each UPA port, processor, U2S, UPA 64S device): * SC_Port_Config registers * SC_Port_Status registers
UPA Data Path Scheduler (DPS)
The DPS is responsible for regulating the flow of data throughout the system. It generates the following: * * * * STP2230SOP (XB1/BMX) crossbar switch commands; S_Replys for all clients; UPA_DATA_STALL signals; UPA_ECC_VAL signals.
DPS contains no software-visible registers.
Memory Controller (MC)
The MC is responsible for controlling the SIMMs. It performs the following functions: * * * * Generates timing for read, write, and refresh; Converts the physical address in the UPA packet into row and column addresses; Maintains the refresh timer; Controls loading and unloading of data from the XB1 read and write buffers.
The PIF forwards memory requests to the MC. The MC communicates with the DPS to schedule delivery of data. The MC contains the following registers:
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* MC_Control 0; and * MC_Control 1 These registers are described in further detail in the USC User Guide.
EBus Interface (EB)
The EB implements an interface to EBus, an asynchronous 8-bit interface controlled by the STP2001 Slave I/O Controller (SLAVIO). Since the USC contains no UPA data path, all reading and writing of internal registers has to take place via EBus. Since all internal registers are 32 bits wide, the EB has to perform packing and unpacking. The EB block implements reset logic and contains a number of global registers. * SC_Control register for controlling resets and logging reset status; * SC_ID register, which contains the USC's JEDEC ID number, implementation and version numbers, and the number of UPA ports that the chip supports; * Performance counters: SC_Perf_Ctrl, SC_Perf0, and SC_Perf1. These counters can be configured to count various events for performance analysis.
Clock and PLL
The USC will operate at a maximum frequency of 100 MHz (10 nanoseconds cycle time). It is a completely synchronous, edge-triggered, register-based design which uses only the rising edge of the clock to update the flip-flops. The chip also contains a phase-locked loop (PLL) to remove the skew introduced by the internal clock distribution network. This improves I/O timing.
JTAG Interface
The USC provides a JTAG interface for full chip scan which is used only for ATPG and in-system interconnect testing. The USC's boundary is shadowed to allow for board-level test.
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ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings [1]
Symbol VDD VCC VIN PD TSTG DC supply voltage DC reference voltage Input voltage (any pin) Continuous power dissipation Storage temperature range -40 Parameter Min 0 0 VSS-0.3 Max 4.1 6.0 VDD + 0.3 2.5 125 Units V V V W C
1. Operation of the device at values in excess of those listed above will result in degradation or destruction of the device. All voltages are defined with respect to ground. Functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Symbol VDD VCC VIN TC TJ DC supply voltage 5V reference voltage Input voltage Case temperature Operating junction temperature VSS-0.3 Parameter Min 3.15 Typ 3.3 5.0 Max 3.45 5.25 VDD + 0.3 70 105 Units V V V C C
Capacitance [1]
Symbol CIN COUT CIO Input capacitance Output capacitance I/O capacitance Parameter Condition Max 10 10 15 Units pF pF pF
1. The parameter values are not tested, they are provided from simulation.
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=
DC Characteristics
Symbol VIL VIH VIL VIH IIN VOL VOH IOZ IDD PD Parameter Input low voltage Input high voltage Input low voltage, CLK + / - Input high voltage, CLK + / - Input current Output low voltage Output high voltage High Z leakage current Supply current Power dissipation leakage current only leakage current only 2.4 10 758 2500 PECL inputs PECL inputs 2.0 VDD-1.81 VDD-1.165 VDD-1.475 VDD-0.88 10 0.4 Conditions Min Max 0.8 Units V V V V A V V A mA mW
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AC CHARACTERISTICS
Nearly all inputs and outputs are registered and are referenced to the PECL differential input clock (CLK+ and CLK-). This clock input controls an on-board PLL. These signals are clocked by the rising edge of CLK+ at the crossover between CLK+ and CLK- (where both signals are at the same voltage). All inputs are applied with a rise and fall time of 1.0 nanosecond (ns). The JTAG signals, are referenced to JTAG_TCK. They are asynchronous signals with respect to CLK+/CLK-. The following signals are asynchronous to CLK + and CLK - and the JTAG clock. They include resets and the EBus Interface signals: EBUS_ADDR[2:0] EBUS_CS EBUS_RD EBUS_WR EBUS_DATA[7:0] P_RESET X_RESET SYS_RESET JTAG_TRST
AC Characteristics, UPA_CLK+ / UPA_CLK -
-83 Parameter tCYCLE tWH tWL tE tE Signal Name CLK+ /CLK- CLK+ /CLK- CLK+ /CLK- CLK+ /CLK- CLK- /CLK- Rising Falling Condition Min 40.0 5.4 5.4 600 600 Max 83.3 Min 40 4.4 4.4 600 600 -100 Max 100.0 Units MHz ns ns ps ps
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AC Characteristics, Signals Referenced to Rising Edge of UPA_CLK
-83 Parameter tSU tH tCO tVO tCO tCO tCO tCO tCO tCO tCO tCO tCO Signal Name UPA signals UPA signals UPA signals UPA signals BMX_CMD0[3:0] BMX_CMD1[3:0] MRB_CTRL[1:0] MWB_CTRL[1:0] MEMADDR[12:0] RAS[3:0] CAS[3:0] WE EBUS_RDY 70 pF 70 pF 70 pF 70 pF 70 pF 70 pF 70 pF 70 pF 70 pF 70 pF 0.5 6.1 6.1 6.1 6.1 6.1 6.1 6.1 6.1 11.9 Condition Min 2.5 0.5 6.1 0.5 4.1 4.1 4.1 4.1 4.1 4.1 4.1 4.1 11.9 Max Min 3.0 0.5 4.1 -100 Max Units ns ns ns ns ns ns ns ns ns ns ns ns ns
AC Characteristics, JTAG_TCK and Signals Referenced to JTAG_TCK
-83 Parameter tCYCLE tWH tWL tE tE tSU tH tSU tH tCO Signal Name JTAG_TCK JTAG_TCK JTAG_TCK JTAG_TCK JTAG_TCK JTAG_TDI JTAG_TDI JTAG_TMS JTAG_TMS JTAG_TDO Rising Falling Wrt rising edge of JTAG_TCK Wrt rising edge of JTAG_TCK Wrt rising edge of JTAG_TCK Wrt rising edge of JTAG_TCK 70 pF; Wrt falling edge of JTAG_TCK 2.5 6.5 2.5 6.5 16.0 30.0 30.0 Condition Min Max 10.0 70.0 70.0 20.0 20.0 2.5 6.5 2.5 6.5 16.0 30.0 30.0 Min -100 Max 10.0 70.0 70.0 20.0 20.0 Units MHz ns ns ns ns ns ns ns ns ns
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Signal Timing Definition
tCYCLE tWH CLK+ 0.0V tE(FALL) 3.0V CLK- 0.0V tsu Input tH VDD/2 tWL tE(RISE) 3.0V
tco tvo
Output
1.5V
Figure 3. Signal Timing Definition
PLL Specifications
PLL and Clock Distribution Circuitry The schematic below shows the PLL scheme inside the USC.
BIED03T FBIN CLK+ CLK- PLL_BYPASS JTAG_TCK P N Z FBOUT
PLL1XSF FBCLK1X REFCLK BYPASS CLK1X
Clock MUX
Clock Buffers
Internal Clock
Clock select from TAP controller
Figure 4. PLL and Clock Distribution Schematic Power Supply Filter The PLL power should be filtered with the following part or equivalent to reduce the system noise injected into the PLL by the system: TDK ACF321825 EMI/RFI filter.
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TIMING DIAGRAMS
Bus Timings
All data transfers have a dead cycle between them, except for back-to-back single writes from the processor to a graphics slave device. The following diagrams show some best-case response timing for the USC. Figure 5 shows the best-case timing for forwarding a PRequest on address bus 0.
UPA_ADDRBUS0
PReq0
PReq1
PReq0
PReq1
UPA_SC_REQ0
Figure 5. Best-Case PRequest-to-PRequest Timing (ABus0 to ABus0)
Figure 6 shows the best-case timing for sending an SRequest that is triggered by a PRequest.
UPA_ADDRBUS0
PReq0
PReq1
SReq0
SReq1
UPA_SC_REQ0
Figure 6. Best-Case PRequest-to-SRequest Timing (ABus0 to ABus0)
Since the USC is always the master of address bus 1 and no arbitration is ever required on that bus, the time it takes for the USC to forward a packet from address bus 0 to address bus 1 is faster than between two devices on address bus 0, as shown in Figure 7.
UPA_ADDRBUS0
PReq0
PReq1
UPA_ADDRBUS1
SReq0
SReq1
Figure 7. Best-Case PRequest-to-SRequest Timing (ABus0 to ABus1)
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Figure 8 and Figure 9 show the best-case timing for non-cacheable single and block read from U2S referenced to the time the P_Reply is issued from the slave. The timing for non-cacheable read from the fast frame buffer (FFB) (UPA64S) is the same, except that it is referenced to a single-cycle P_RASB instead of the two-cycle P_RAS/P_RAB.
0 UPA_PREPLY UPA_SREPLY to master UPA_SREPLY to slave BMX_CMD DATA_STALL UPA_DATA 64 UPA_DATA 128 X_IPS 1 P_RAS S_SRS S_RAS 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
Figure 8. Best-Case Timing for Noncached Single Read, UPA64 -> UPA128
0 UPA_PREPLY UPA_SREPLY to master UPA_SREPLY to slave BMX_CMD DATA_STALL (CPU) UPA_DATA 64 UPA_DATA 128 X_IPB 1 P_RAB S_SRB S_RBU 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
Figure 9. Best-Case Timing for Noncached Block Read, UPA64 -> UPA128 Figure 10 and Figure 11 show the best-case timing for a non-cacheable single and block write to the U2S. A non-cacheable write to the FFB has similar timing, except that the time it takes to forward the PRequest is slightly less.
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0 UPA_ADDRBUS0 UPA_SREPLY to master UPA_SREPLY to slave BMX_CMD DATA_STALL UPA_DATA 64 UPA_DATA 128
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
S_WAS S_SWS X_PIS
Figure 10. Best-Case Timing for Non-Cached Single Write, UPA128 -> UPA64
0 UPA_ADDRBUS0 UPA_SREPLY to master UPA_SREPLY to slave BMX_CMD DATA_STALL UPA_DATA 64 UPA_DATA 128 X_PIB S_WAB S_SWB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
Figure 11. Best-Case Timing for Non-Cached Block Write, UPA128 -> UPA64 Figure 12 and Figure 13 show a U2S single and block read from the FFB, referenced to the P_Reply from the FFB.
0 UPA_PREPLY UPA_SREPLY to master UPA_SREPLY to slave BMX_CMD DATA_STALL UPA_DATA 64 UPA_DATA 128 1 P_RASB S_RAS S_SRS 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
Figure 12. Best-Case Timing for Non-Cached Single Read, UPA64 -> UPA64
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0 UPA_PREPLY UPA_SREPLY to master UPA_SREPLY to slave BMX_CMD DATA_STALL UPA_DATA 64 UPA_DATA 128
1 P_RASB
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
S_RAB S_SRB
Figure 13. Best-Case Timing for Noncached Block Read, UPA64 -> UPA64 Figure 14 and Figure 15 show the best-case timing for a U2S non-cacheable single and block write to FFB.
0 UPA_ADDRBUS UPA_SREPLY to master UPA_SREPLY to slave BMX_CMD DATA_STALL UPA_DATA 64 UPA_DATA 128 BUS0 BUS1 S_WAS S_SWS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
Figure 14. Best-Case Timing for Noncached Single Write, UPA64 -> UPA64
0 UPA_ADDRBUS UPA_SREPLY to master UPA_SREPLY to slave BMX_CMD DATA_STALL UPA_DATA 64 UPA_DATA 128
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
BUS0
BUS1
S_WAB S_SWB
Figure 15. Best-Case Timing for Noncached Block Write, UPA64 -> UPA64
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Figure 16 and Figure 17 show the nominal timing for a U2S non-cacheable single and block read from the processor.
0 UPA_PREPLY UPA_SREPLY to master UPA_SREPLY to slave BMX_CMD DATA_STALL UPA_DATA 64 UPA_DATA 128 S_SRS X_PIS 1 P_RASB S_RAS 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
Figure 16. Best-Case Timing for Noncached Single Read, UPA128 -> UPA64
0 UPA_PREPLY UPA_SREPLY to master UPA_SREPLY to slave BMX_CMD DATA_STALL UPA_DATA 64 UPA_DATA 128
1 P_RASB
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
S_RAB S_SRB X_PIB
Figure 17. Best-Case Timing for Noncached Block Read, UPA128 -> UPA64
Note: Timing diagrams for U2S non-cacheable single and block write to the processor are not shown because such transactions are dropped by the USC. Figure 18 shows the "fast path" timing for memory reads issued from the processor. Fast paths are characterized by row address valid one cycle earlier than that of normal paths. The fast path is only available for reads issued from the processor's master class 0. It is not available for writes or for any accesses from the U2S. Normal paths are used for all transactions that are not processor reads from memory, for example, DMA, memory writes, etc. See Figure 22 and Figure 23 for a graphic representation of fast paths and normal paths. Fast path is not implemented for processor writes because for processor transaction type P_WRI_REQ (described in the UPA specification) we need to examine the IVA bit (state bit embedded in the transaction packet, as described in the UPA specification) before launching the request to memory, and the IVA bit is in the second half of the PRequest packet. P_WRB_REQ (described in the UPA specification) almost always follows a victimizing read, and this can be overlapped with the read. Accesses from the U2S are less latency sensitive. Since the fast path is very timing critical and adds additional complexity to the logic, it is not implemented for the U2S.
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)
UPA_ADDRBUS0
PReq0
PReq1
MEMADDR[12:0]
Row Address
RAS
Figure 18. Best-Case PRequest-to-Memory Request Timing, Read (Fast Path) Figure 19 shows a read or write issued through the "normal path."
UPA_ADDRBUS0
PReq0
PReq1
MEMADDR[12:0]
Row Address
RAS
Figure 19. Best-Case PRequest-to-Memory Request Timing (Normal Path)
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RAS
RP
RAS
CAS
Fixed at Two Clocks Fixed at One Clock
Figure 21. Basic Refresh Timing 1. RAS is the minimum RAS timing. 2. RP is the RAS-precharge timing.
UPA-to-Memory Timing
Figure 22 and Figure 23 show the minimum time for a UPA memory request packet issued on the UPA address bus pins to traverse the USC and appear on the USC's memory outputs, assuming that the USC is idle.
UPA_ADDRBUS0
MEMADDR[12:0]
Row Address
RAS
Figure 22. Best-Case UPA-to-Memory Timing (Fast Path)
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UPA_ADDRBUS0
MEMADDR[12:0]
Row Address
RAS
Figure 23. Best-Case UPA-to-Memory Timing (Normal Path) Note: Fast path timing is only applicable for memory reads issued from the processor. All other memory accesses use the normal path.
Default Memory Timing
Figure 24 through Figure 28 show the default timing after power on. These are the slowest, most conservative timings possible and are guaranteed to work at any frequency.
0 MEMADDR RAS CAS WE MRB_CTRL UPA_SREPLY BMX_CMD MEMDATA UPA_DATA UPA_DATA_STALL 1 2 Row 3 4 5 6 Column 0 7 8 9 10 11 12 13 14 15 16 17 18 19
Column 1
Figure 24. Default Memory CPU Read Timing
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0 MEMADDR RAS CAS WE MRB_CTRL UPA_SREPLY BMX_CMD UPA_DATA (CPU) MEMDATA UPA_DATA_STALL
1
2
3 Row
4
5
6
7
8
9
10
11
12
13 Column 1
14
15
16
17
18
19
Column 0
RAS High for Five Clocks Before Next Transaction
Figure 25. Default Memory CPU Write Timing
0 MEMADDR RAS CAS WE MRB_CTRL UPA_SREPLY BMX_CMD MEMDATA UPA_DATA UPA_DATA_STALL
1
2 Row
3
4
5
6 Column 0
7
8
9
10
11
12
13
14
15
16
17
18
19
Column 1
Figure 26. Default Memory U2S Read Timing
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0 MEMADDR RAS CAS WE MRB_CTRL UPA_SREPLY BMX_CMD UPA_DATA (U2S) MEMDATA UPA_DATA_STALL
1
2
3
4 Row
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
Column 0
Column 1
Figure 27. Default Memory U2S Write Timing
0 MEMADDR RAS CAS WE MWB_CTRL MRB_CTRL MEMDATA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
Figure 28. Default Refresh Timing
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83.3 MHz (12 ns) Timings
0 MEMADDR RAS CAS WE MRB_CTRL UPA_SREPLY BMX_CMD MEMDATA UPA_DATA UPA_DATA_STALL 1 2 Row 3 4 5 6 7 8 9 10 Column 1 11 12 13 14 15 16 17 18 19
Column 0
Figure 29. 83.3 MHz CPU Read Timing
0 MEMADDR RAS CAS WE MWB_CTRL UPA_SREPLY BMX_CMD UPA_DATA (CPU) MEMDATA UPA_DATA_STALL 1 2 3 Row 4 5 6 7 8 9 10 11 12 Column 1 13 14 15 16 17 18 19
Column 0
Figure 30. 83.3 MHz CPU Write Timing
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0 MEMADDR RAS CAS WE MRB_CTRL UPA_SREPLY BMX_CMD MEMDATA UPA_DATA UPA_DATA_STALL
1
2 Row
3
4
5
6
7
8
9
10 Column 1
11
12
13
14
15
16
17
18
19
Column 0
Figure 31. 83.3 MHz U2S Read Timing
0 MEMADDR RAS CAS WE MWB_CTRL UPA_SREPLY BMX_CMD UPA_DATA (U2S) MEMDATA UPA_DATA_STALL 1 2 3 4 Row 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
Column 0
Column 1
Figure 32. 83.3 MHz U2S Write Timing
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July 1997
USC Uniprocessor System Controller
STP2200ABGA
0 MEMADDR RAS CAS WE MWB_CTRL MRB_CTRL MEMDATA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
Figure 33. 83.3 MHz Refresh Timing
71.4 MHz (14 nanoseconds) Timings
0 MEMADDR RAS CAS WE MRB_CTRL UPA_SREPLY BMX_CMD MEMDATA UPA_DATA UPA_DATA_STALL 1 2 Row 3 4 5 Column 0 6 7 8 9 Column 1 10 11 12 13 14 15 16 17 18 19
Next Row
Figure 34. 71.4 MHz CPU Read Timing
July 1997
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STP2200ABGA
USC Uniprocessor System Controller
0 MEMADDR RAS CAS WE MWB_CTRL UPA_SREPLY BMX_CMD UPA_DATA (CPU) MEMDATA UPA_DATA_STALL
1
2
3 Row
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
Column 0
Column 1
Figure 35. 71.4 MHz CPU Write Timing
0 MEMADDR RAS CAS WE MRB_CTRL UPA_SREPLY BMX_CMD MEMDATA UPA_DATA UPA_DATA_STALL 1 2 Row 3 4 5 Column 0 6 7 8 9 10 11 12 13 14 15 16 Next Row 17 18 19
Column 1
Figure 36. 71.4 MHz U2S Read Timing
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July 1997
USC Uniprocessor System Controller
STP2200ABGA
0 MEMADDR RAS CAS WE MWB_CTRL UPA_SREPLY BMX_CMD UPA_DATA (U2S) MEMDATA UPA_DATA_STALL
1
2
3
4 Row
5
6
7
8
9
10
11
12
13
14 Column 1
15
16
17
18
19
Column 0
Figure 37. 71.4 MHz U2S Write Timing
0 MEMADDR RAS CAS WE MWB_CTRL MRB_CTRL MEMDATA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
Figure 38. 71.4 MHz Refresh Timing
July 1997
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STP2200ABGA
USC Uniprocessor System Controller
Minimum Timings
Figure 39 through Figure 43 show the absolute minimum timing that the memory controller is capable of generating.
0 MEMADDR RAS CAS WE MWB_CTRL UPA_SREPLY BMX_CMD MEMDATA UPA_DATA (CPU) UPA_DATA_STALL 1 Row 2 3 4 Column 0 5 6 7 Column 1 8 9 10 11 12 13 14 15 16 17 18 19
Next Row
Figure 39. Minimum CPU Read Timing
0 MEMADDR RAS CAS WE MWB_CTRL UPA_SREPLY BMX_CMD UPA_DATA (CPU) MEMDATA UPA_DATA_STALL
1
2
3 Row
4
5
6
7
8 Column 0
9
10
11
12
13
14
15
16
17
18
19
Column 1
Figure 40. Minimum CPU Write Timing
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July 1997
USC Uniprocessor System Controller
STP2200ABGA
0 MEMADDR RAS CAS WE MRB_CTRL UPA_SREPLY BMX_CMD MEMDATA UPA_DATA UPA_DATA_STALL
1 Row
2
3
4 Column 0
5
6
7 Column 1
8
9
10
11
12
13
14
15
16
17
18
19
Next Row
Figure 41. Minimum U2S Read Timing
0 MEMADDR RAS CAS WE MWB_CTRL UPA_SREPLY BMX_CMD UPA_DATA (CPU) MEMDATA UPA_DATA_STALL
1
2
3
4 Row
5
6
7
8
9
10 Column 0
11
12
13
14
15
16
17
18
19
Column 1
Figure 42. Minimum U2S Write Timing
July 1997
31
STP2200ABGA
USC Uniprocessor System Controller
0 MEMADDR RAS CAS WE MWB_CTRL MRB_CTRL MEMDATA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
Figure 43. Minimum Refresh Timing
32
July 1997
USC Uniprocessor System Controller
STP2200ABGA
EBus Timing
Figure 44 and Figure 45 show external timing for EBus accesses.
EBUS_CS
EBUS_ADDR[2:0]
EBUS_RD
EBUS_WR
EBUS_RDY
EBUS_DATA[7:0]
Figure 44. External EBus Read Timing
EBUS_CS
EBUS_ADDR[2:0]
EBUS_WR
EBUS_RD
EBUS_DATA[7:0]
EBUS_RDY
Figure 45. External EBus Write Timing
July 1997
33
STP2200ABGA
USC Uniprocessor System Controller
PACKAGE INFORMATION
225-Pin Plastic Ball Grid Array (ABGA) Pin Assignments
Pin A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 VSS UPA_PREPLY1_1 JTAG_TRST VDD JTAG_TDI X_RESET VSS PLL_VDD VDD UPA_SREPLY1_2 UPA_SREPLY1_0 VSS EBUS_RD EBUS_DATA_6 VDD UPA_SREPLY0_1 UPA_SREPLY0_4 UPA_SREPLY0_3 JTAG_TMS JTAG_TDO UPA_DATA_STALL1 PLL_VSS UPA_DATA_STALL0 UPA_SREPLY1_4 UPA_RESET_1 EBUS_WR UPA_RESET_0 EBUS_DATA_1 EBUS_DATA_3 EBUS_DATA_0 BMX_CMD1_3 MWB_CTRL0 MRB_CTRL1 UPA_PREPLY1_2 JTAG_TCK UPA_XIR SYS_RESET CLK- UPA_ECC_VAL_1 UPA_SREPLY1_3 EBUS_DATA_5 EBUS_DATA_7 EBUS_ADDR_2 UPA_SREPLY2_0 UPA_PREPLY2_0 Signal Name Pin D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 VDD BMX_CMD0_2 UPA_SREPLY0_0 UPA_PREPLY1_4 UPA_PREPLY1_0 PLL_BYPASS CLK+ UPA_ECC_VAL_0 UPA_SREPLY1_1 EBUS_RDY EBUS_DATA_4 EBUS_ADDR_0 UPA_ADDR1_VAL1 5V_REF VSS BMX_CMD0_1 BMX_CMD1_1 BMX_CMD0_3 MRB_CTRL0 UPA_PREPLY1_3 P_RESET VDD VDD VDD EBUS_CS EBUS_ADDR_1 UPA_SREPLY2_1 UPA_PREPLY2_1 UPA_ADDRBUS1_00 UPA_ADDRBUS1_02 BMX_CMD0_0 CAS3 BMX_CMD1_2 MWB_CTRL1 UPA_SREPLY0_2 PM_OUT VSS VSS VSS EBUS_DATA_2 UPA_SREPLY2_2 UPA_ADDRBUS1_01 UPA_ADDRBUS1_06 UPA_ADDRBUS1_03 UPA_ADDRBUS1_04 Signal Name Pin G1 G2 G3 G4 G5 G6 G7 G8 G9 VSS WE BMX_CMD1_0 CAS2 VDD VSS VSS VSS VSS Signal Name Pin K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 M1 M2 M3 M4 M5 M6 M7 M8 M9 Signal Name DEBUG_2 [1] MEMADDR_12 DEBUG_1 [1] MEMADDR_10 MEMADDR_4 UPA_ADR0_PAR0 VSS VSS VSS UPA_ADDRBUS0_00 UPA_ADDRBUS1_27 UPA_ADDRBUS1_19 UPA_ADDRBUS1_21 UPA_ADDRBUS1_16 UPA_ADDRBUS1_14 MEMADDR_11 MEMADDR_9 MEMADDR_6 MEMADDR_0 UPA_PREPLY0_2 UPA_ADDRBUS0_33 VDD VDD VDD UPA_ADDRBUS0_04 UPA_ADDR0_VAL0_0 UPA_ADDRBUS1_22 UPA_ADDRBUS1_24 UPA_ADDRBUS1_20 UPA_ADDRBUS1_18 VSS MEMADDR_8 MEMADDR_3 NC UPA_PREPLY0_0 UPA_ADDRBUS0_30 UPA_ADDRBUS0_26 UPA_ADDRBUS0_22 UPA_ADDRBUS0_14 Pin N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 Signal Name MEMADDR_5 MEMADDR_7 MEMADDR_1 DEBUG_3 [1] UPA_ADDRBUS0_31 UPA_ADDRBUS0_24 UPA_ADDRBUS0_21 UPA_ADDRBUS0_18 UPA_ADDRBUS0_17 UPA_ADDRBUS0_10 UPA_ADDRBUS0_06 UPA_ADDRBUS0_05 UPA_REQIN0_1 UPA_ADDRBUS1_26 UPA_ADDRBUS1_23 MEMADDR_2 UPA_PREPLY0_4 UPA_PREPLY0_3 UPA_ADDRBUS0_34 UPA_ADDRBUS0_29 UPA_ADDRBUS0_28 UPA_ADDRBUS0_23 UPA_ADDRBUS0_20 UPA_ADDRBUS0_15 UPA_ADDRBUS0_13 UPA_ADDRBUS0_09 UPA_ADDRBUS0_07 UPA_ADDRBUS0_01 UPA_REQIN0_0 UPA_SC_REQ0 VDD UPA_PREPLY0_1 UPA_ADDRBUS0_32 VSS UPA_ADDRBUS0_27 UPA_ADDRBUS0_25 VDD UPA_ADDRBUS0_19 VSS UPA_ADDRBUS0_16 UPA_ADDRBUS0_11 VDD UPA_ADDRBUS0_08 UPA_ADDRBUS0_02 VSS
G10 VSS G11 VDD G12 UPA_ADDRBUS1_05 G13 UPA_ADDRBUS1_09 G14 UPA_ADDRBUS1_07 G15 VDD H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 CAS0 RAS3 CAS1 DEBUG_0 [1] VDD VSS VSS VSS VSS VSS VDD UPA_ADDRBUS1_13 UPA_ADDRBUS1_12 UPA_ADDRBUS1_08 UPA_ADDRBUS1_10 VDD RAS1 RAS2 RAS0 VDD VSS VSS VSS VSS VSS VDD UPA_ADDRBUS1_15 UPA_ADDRBUS1_17 UPA_ADDRBUS1_11 VSS
M10 UPA_ADDRBUS0_12 M11 UPA_ADDRBUS0_03 M12 UPA_ADDR0_VAL0_1 M13 UPA_ADDRBUS1_28 M14 UPA_ADDRBUS1_25 M15 VDD
1. DEBUG pins are used for internal debug only and are not used in a system implementation.
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July 1997
USC Uniprocessor System Controller
STP2200ABGA
225-Pin Plastic ABGA Package Dimensions
0.35 C 1.73 0.10 0.56 0.06 -C0.60 0.05 TYP
27.00 0.10 Square 24.00 0.10 Square 13.50 0.10 TYP 12.00 0.10 TYP
Seating Plane
3.00 TYP
14 Spaces @ 1.50 = 21.00
3.00 TYP
15 14 13 12 11
14 Spaces @ 1.50 = 21.00
10 9 8 7 6 5 4 3 2
25 Appro x.
1
Position A1 Indicator 0.78 DIA Approx. (Gold plated)
0.15
C
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
Solder ball grid array coordinates are for reference only
Notes:
1. Drawing is not to scale. 2. Unless otherwise specified, all dimensions are in millimeters. Nonlimited dimensions other than size of raw material shall be held as follows when expressed: 10-2 decimal places, 0.13 as angles, 10-3 decimal places 3. It is imperative that measures be taken during assembly, handling, etc. to prevent the possibility of damage to devices by static electric discharge. 4. The flatness of the overmold surface in the center 10.16 mm DIA area, shall be within 0.076 mm.
July 1997
35
STP2200ABGA
USC Uniprocessor System Controller
36

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